In recent years, system-in-package technology which realizes a high-performance system in a short period by high-densely packaging a plurality of semiconductor chips having integrated circuits mounted thereon attracts attention, and manufacturers respectively suggest various packaging structures. Particularly, stacked package which can significantly make the size smaller by three-dimensionally stacking a plurality of semiconductor chips has actively developed.
For example, as disclosed in Japanese Patent Application Laid-Open Publication No. 11-204720 (Patent Document 1), the three-dimensionally stacked semiconductor chips and the package substrate are electrically connected mainly by wire bonding. Therefore, the upper chip of the stacked semiconductor chips is required to be smaller than the lower chip. When chips having similar sizes are stacked, it is required to ensure wire-bonding areas by forming a structure with spacers between chips. This kind of electrical connection of wire bonding has high degree of freedom in routing and so it is a very effective way to realize electrical connections between a plurality of semiconductor chips in short TAT (Turn Around Time) and at low cost.
However, in wire bonding connection, it is required to bond all of the wirings from a plurality of chip electrodes to the package substrate once and then wiring again to another chip. Accordingly, there have been problems of very long connection length between chips and of very high density of wiring on the package substrate. Due to the problems, inductance between chips increases so that high-speed transmission gets to be difficult. And moreover, yield is reduced as density on the package substrate gets higher, and the substrate cost may be increased.
For these problems in wire bonding, a method to form electrodes penetrating through the chip and connect upper and lower chips is suggested. For example, Japanese Patent Application Laid-Open Publication No. 2004-342990 (Patent Document 2) discloses a method to form through-hole electrodes of plate-filing type from the back surface of wafer with respect to a semiconductor wafer fixed on a holding member and thinned. Japanese Patent Application Laid-Open Publication No. 2005-340389 (Patent Document 3) discloses a structure in which through-hole electrodes in hole-shape without filling plate from the back surface of wafer are formed and metal bumps are mechanically pressurized and filled inside the holes to connect chips.